The simulator described here-LOSIM(LOgic SIMulator)-was developed to verify the logic design for VLSI(Very Large Scale Integrated) circuits at mixed level. In this paper, we present a modeling approach to obtain more accurate results than conventional logic simulators [5-6,9] for general elements, functional elements, transmission gates and tri-state gates using eight signal values and two gignal strengths. LOSIM has the capability which can perform timing and hazard analysis by using assignable rise and fall delays. We also prosent an efficient algorithm to accurately detectdynamic and static hazards which may be caused by the circuit delays. Our approach is based on five logic values and the scheduled time. LOSIM has been implemented on a UN-3/160 workstation running Berkeley 4.2 UNIX, and the program is written in C language. Static RAM cell and asynchronous circuit are illustrated as an example.