In this dissertation, the same reading and writing operation of general SRAM, the algonthm and hardware of 8 bit $ imes$16 word CAM(Content Addressable Memory) which carry out the parallel that search is presented. The designed CAM chip consists of five functional blocks (CAM cell array, Address Deceden, Address Encoden. Data Selector, Sense Amplifier). The smulation is performed using logic smmulator on Apollo workstation and PSPICE eitcut simulation on PC/AT. The designed CAM was fabricated by 3um CMOS N Well process (ETRI) design nitles and testing was performed.