This paper deals with a detailed analysis of CMOS latch up dependancies on the layout and geo-metrical demensions on the mask using same materials and same processes. For this purpose, six different layout models depending upon the N+ / P+ spacing and three different guard ring models have been gesigned, fabricated, and tested. As a result, common emitter current gain, shunt resistance, and holeing current versus N+/P+ spacing have been measured and analyzed experimentally. Also the fact that guard ring is sffective in reducing the latchup possibility has been verified through this study.