A new High level hardware Description Language, ASPHODEL(Algorithm Synthesis Pascal Hardware for Optimal Design and Efficient Language), and its algorithm compiler for high level synthesis are described in this paper. The new HDL, appropriated to the description of algorithmic level and lower, models VLSI circuits as an abstracted block which is consisted of input/output ports and hierachical processors to control VLSI complexities with efficiency. Also, in order to improve the descriptive power, popular Pascal programming language is modified to build ASPHODEL syntax rules. ASPHODEL algorithm compiler generates an intermediate form through lexical and syntax analysis from ASPHODEL source codes. To show the validation of presented language and its compiler, those are applied to practical design examples.