The characteristics of the internal circuits and the load capacitance should be included to optimize the size of BiCMOS buffer. In order to get the optimum size and delay time of the BiCMOS buffer, new size plane is suggested. By using the size plane, the optimum characteristics of CMOS buffer according to the number of stages can be obtained. From this method, delaytime, .tau.$_{D}$, is obtained 2.39 nsec with $V_{var}$=5V, $C_{L}$=5pF, W=30.mu.m and $A_{e}$=135.mu. $m^{2}$.>..>...>.