- 새로운 동적 CMOS 논리 설계방식을 이용한 고성능 32비트 가산기 설계
- ㆍ 저자명
- 김강철,한석붕
- ㆍ 간행물명
- 電子工學會論文誌. Jounnal of the Korea institute of telematics and electronics. A. A
- ㆍ 권/호정보
- 1996년|3호|pp.187-195 (9 pages)
- ㆍ 발행정보
- 대한전자공학회
- ㆍ 파일정보
- 정기간행물| PDF텍스트
- ㆍ 주제분야
- 기타
This paper proposes two new dynamic CMOS logic styles, called ZMODL (zipper-MODL) and EZMODL (enhanced-ZMODL), which can reduce more area dnd propagation delya than conventional MODL (multiple output domino logic). The 32-bit CLAs(carry look-ahead adder) are designed by ZMODL, EZMODL circuits, and their operations are verified by SPICE 3 with 2$mu$ double metal CMOS parameters. The results shwo that the CLA designed by EZMODL circuit has achived 32-bit additin time of less than 4.8NS with VDD=5.0V and 8% of transistors cn be redcued, compared to the CLA designed by MODL. The EZMODL logic style can improve the performance in the high-speed computing circuits depending on the degree of recurrence.