This paper presents a new symmetrical routing architecture for FPGA and an efficient routing algorithm for the architecture. The routing architecture adopts the segmented wires and the improved switch modules. Segmetned wires construct routing channels which pass through the chip in vertical and horizontal directions. To maximize the utility of a track, a track in each switch module can be separated in two part using a programmable switch to route two different net. The proposed routing algorithm finds all assignable tracks for a given net and selects the best track from assignable tracks to minimize the number of programmable switches and the unused portion of the wire segments. In order to stabilize the perfomrance of the algorithm, the routing order is defined by weighted sum of the number of wire segment, the length of wire segmetn, and the number of pin. Experimental results show that routability is improved dramatically and the number of crossing switches are reduced about 40% compared with the previous works.