- Smart power IC용 RESURF EDMOSFETs의 제조공정과 최적설계
- ㆍ 저자명
- 정훈호,권오경
- ㆍ 간행물명
- 電子工學會論文誌. Jounnal of the Korea institute of telematics and electronics. A. A
- ㆍ 권/호정보
- 1996년|7호|pp.176-184 (9 pages)
- ㆍ 발행정보
- 대한전자공학회
- ㆍ 파일정보
- 정기간행물| PDF텍스트
- ㆍ 주제분야
- 기타
To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${Omega}{cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${Omega}{cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.