This paper describes the hardware architecture and implementation trade-offs of the Grand Alliance HDTV video encoder system. The implemented video encoder accepts video in 1125 line(30Hz) interlaced format, and produces a bit-stream compliant with the motion picture experts group version 2(MPEG-2) standards. The encoder processing includes large- area motion estimation and an advanced rate control mechanism. To keep the system complexity realizable, we adopt a fast hierarchical motion estimation method and developed its hardware architecture. Furthermore an adaptive perceptual quantization method is adopted to improve the perceptual quality. The developed system Is based on the 4-way parallel processing architecture and is implemented by using programmable IC, memory IC, and special-purpose processors such as DCT and motion estimation processors.