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Effects of Offset Gate on Programing Characteristics of Triple Polysilicon Flash EEPROM Cell
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  • Effects of Offset Gate on Programing Characteristics of Triple Polysilicon Flash EEPROM Cell
  • Effects of Offset Gate on Programing Characteristics of Triple Polysilicon Flash EEPROM Cell
저자명
Kim. Nam-Soo,Choe. Yeon-Wook,Kim. Yeong-Seuk
간행물명
Journal of electrical engineering and information science
권/호정보
1997년|2권 3호|pp.132-138 (7 pages)
발행정보
한국정보과학회
파일정보
정기간행물|ENG|
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이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.