By utilizing the technique to monitor the DC cell node voltages through circuit simulation, degradation of the static read operating margin In high load-resistor SRAM cell was examined, which is caused by parasitic resistances and transistor asymmetries in this cell structure. By selectively adding the parasitic resistances to an ideal cell, the influence of each parasitic resistance on the operating margin was examined, and then the cases with parasitic resistances in pairs were also examined. By selectively changing the channel width of cell transistors to generate cell asymmetry, the influence of cell asymmetry on the operating margin was also examined. Analyses on the operating margins were performed by comparing the supply voltage values at which two cell node voltages merge to a single value and the differences of cell node voltages at VDD=5V in the simulated node voltage characteristics. By determining the parasitic resistances and the transistor asymmetries which give the most serious effect on the static read-operation of SRAM cell from this analysis based on circuit simulated, a criteria was provided, which can be referred in the design of new SRAM cell structures.