In this paper a double edge triggered (DET) filp-flop is proposed which changes its output state at both the positive and the negative edge transitions of the triggering input. DET filp-flop has advantages in terms of speed and power dissipation over single edge triggered (SET) filp-flop has proposed DET flip-flop needs only 12 MOS transistors and can operate at clock speed of 500 MHz. Also, the power dissipation has decreased about 33% in comparison to SET flip-flop.