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루프를 효과적으로 처리하는 PASC 프로세서 구조
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  • 루프를 효과적으로 처리하는 PASC 프로세서 구조
  • PASC Processor Architecture for Enhanced Loop Execution
저자명
지승현,박노광,전중남,김석일,Ji. Seung-Hyeon,Park. No-Gwang,Jeon. Jung-Nam,Kim. Seok-Il
간행물명
정보처리논문지
권/호정보
1999년|6권 5호|pp.1225-1240 (16 pages)
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한국정보처리학회
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이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

This paper proposes PASC(PArtitioned SCHeduler) processor architecture that equips with a number of functional unit and an individual scheduler paris. Every scheduler of the PASC processor can determine whether a unit instruction can be issued to the associated functional unit or it is to be waited until next cycle caused by a resource collision or data dependencies. In the PASC processor, only the functional unit with a resource collision or data dependencies waits by executing a NOP(No OPeration) instruction and the other functional units execute their own instructions. Therefore we can expect the code compaction effect on the PASC processor. Thus, the last instruction of a loop at certain iteration and the very first instruction of the loop at the next iteration can be scheduled simultaneously if the two instructions do not incur any resource collision or data dependencies. Therefore, we can expect that such two instructions without any resource collision and data dependencies are packed into the same very long instruction word and thus, the two instructions are executed concurrently at run time. As a result, we can shorten execution cycles of a loop comparing to the execution of the loop on a traditional VLIW or SVLIW processor architecture. Simulation result also promises faster execution of loops on a PASC processor architecture than those on a VLIW and SVLIW processor architecture.