A multiple vector reductive processing occurs during the vector inner product operation ([C] = [A] $igodot$,$square$ [B]) and proceeds at the hardware dyadic pipeline unit. Every scalar result has to be generated with the component merging delay time in the multiple vector reduction($igodot$). In this paper we propose a new design method by which the component merging time could be eliminated from the multiple reduction and the scalar results from the reduction($igodot$) could be generated nearly in the almost same condensed time as the input components are fel>ded in the dyadic pipeline unitlo) or the output components are drained out of the dyadic pipeline unit($square$), so called a dedicated chained pipeline unit for only a inner product operation.