This paper proposes a design method that can minimize the power dissipation of CMOS digital circuits without affecting their optimal operation speeds. The proposed method is based on genetic algorithms(GAs) combined to the retiming technique, a circuit transformation technique of repositioning flip-flops. The proposed design method consists of two phases: the phase of retiming for optimizing clock periods and the phase of GA retiming for minimizing power dissipation. Experimental results using Synopsys Design Analyzer show that the proposed design method can reduce the critical path delay of example circuits by about 30-50% and improve the dynamic power performance of the circuits by about 1.4~18.4%.