In this paper we propose an efficient implementation technique for cyclic extension in VDSL(Very High bit-rate Digital Subscriber Line) systems using Zipper duplexing and analyze its performances under typical telephone channel environments. In Zipper-based VDSL systems each DTM(discrete-multitone) block is appended by both cyclic prefix(CP) and cyclic suffix(CS). The CP is inserte to prevent both intersymbol interference (ISI) and iterchannel interference (ICI) while the CS is appended to ensure orthogonality between the upstream and downstream carriers thus preventing near-end crosstalk (NEXT). However in order to implement the CP in the transmitter side of the VDSL system an additional hardware is required to append the latter part of each DMT symbol to the beginning of the DMT symbol. In this paper we propose a VDSL system with Zipper duplexing using only CS to reduce hardware complexity (memory and processing delay) required for implementation of CP. It is shown by computer simulation that the proposed approach has the same capacity under typical channel environments as the previous Zipper-based VDSL system using both CP and CS. even with a significantly lower hardware complexity.