The box capacitor structure with HSG-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a $0.4820mum^2$ for 128Mbit DRAM. An HSG-Si formation technology with seeding method, which employs Si2H6 molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.The box capacitor structure with HSG-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a $0.4820mum^2$ for 128Mbit DRAM. An HSG-Si formation technology with seeding method, which employs Si2H6 molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.