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Improved Transmitter Power Efficiency using Cartesian Feedback Loop Chip
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  • Improved Transmitter Power Efficiency using Cartesian Feedback Loop Chip
  • Improved Transmitter Power Efficiency using Cartesian Feedback Loop Chip
저자명
Chong. Young-Jun,Lee. Il-Kyoo,Oh. Seung-Hyeub
간행물명
Journal of the Korea Electromagnetic Engineering Society
권/호정보
2002년|2권 2호|pp.93-99 (7 pages)
발행정보
한국전자파학회
파일정보
정기간행물|ENG|
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기타
이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

The Cartesian loop chip which is one of key devices in narrow-band Walky-Talky transmitter using RZ-SSB modulation method was designed and implemented with 0.35 Um CMOS technology. The reduced size and low cost of transmitter were available by the use of direct-conversion and Cartesian loop chip, which improved the power efficiency and linearity of transmitting path. In addition, low power operation was possible through CMOS technology. The performance test results of transmitter showed -23 dBc improvement of IMD level and -30 dEc below suppression of SSB characteristic in the operation of Cartesian loop chip (closed-loop). At that time, the transmitting power was about 37 dBm (5 W). The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.