New layout methods for implementing MOS switches of ultra low channel resistance are presented. These area-effective layout methods include the waffle structure, zipper structure, star zag structure and fingered waffle structure. The design equations for these new layout structures are analyzed. The area-effectiveness of these structures is compared with that of the conventional alternating bar structure. MOS switches of the waffle structure were fabricated using a standard 0.25um CMOS process. The experimental characterization results of the fabricated MOS switches are presented. The analytical comparison and experimental results show that area reductions over 40% are achievable with the new structures.