Influence of post gate oxidation anneal on Negative Bias Temperature Instability (NBTI) of PMOSFE has been investigated. At oxidation anneal temperature raised above 950$^{circ}$C, a significant improvement of NBTI was observed which enables to reduce PMO V$\_$th/ shift occurred during a Bias Temperature (BT) stress. The high temperature anneal appears to suppress charge generations inside the gate oxide and near the silicon oxide interface during the BT stress. By measuring band-to-band tunneling currents and subthreshold slopes, reduction of oxide trapped charges and interface states at the high temperature oxidation anneal was confirmed.