In this paper, new design equations based on the pole-zero analysis for multi-layered interdigital stripline linear group delay bandpass filter with tap input ports are presented. As a design example, a four-pole group delay filter with center frequency of 2.14GHz, bandwidth of 160MHz, and group delay variation of $pm$0.1nS for LTCC technology or multilayered PCB technology is designed. In the design process, it is not necessary to simulate the entire structure, as the simulation of half structures is sufficient. Good results can be attained after the optimizing process was performed three times using the proposed equations and a commercial EM simulator.