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서지반출
An FPGA Design of High-Speed Turbo Decoder
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취소
  • An FPGA Design of High-Speed Turbo Decoder
  • An FPGA Design of High-Speed Turbo Decoder
저자명
Jung. Ji-Won,Jung. Jin-Hee,Choi. Duk-Gun,Lee. In-Ki
간행물명
한국통신학회논문지. The Journal of Korea Information and Communications Society. 통신이론 및 시스템
권/호정보
2005년|30권 |pp.450-456 (7 pages)
발행정보
한국통신학회
파일정보
정기간행물|ENG|
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기타
이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
서지반출

기타언어초록

In this paper, we propose a high-speed turbo decoding algorithm and present results of its implementation. The latency caused by (de)interleaving and iterative decoding in conventional MAP turbo decoder can be dramatically reduced with the proposed scheme. The main cause of the time reduction is to use radix-4, center to top, and parallel decoding algorithm. The reduced latency makes it possible to use turbo decoder as a FEC scheme in the real-time wireless communication services. However the proposed scheme costs slight degradation in BER performance because the effective interleaver size in radix-4 is reduced to an half of that in conventional method. To ensure the time reduction, we implemented the proposed scheme on a FPGA chip and compared with conventional one in terms of decoding speed. The decoding speed of the proposed scheme is faster than conventional one at least by 5 times for a single iteration of turbo decoding.