- 나노 CMOS 소자 적용을 위한 질소 분위기에서 형성된 질화막을 이용한 폴리실리콘 적층 구조
- ㆍ 저자명
- 호원준,이희덕,Ho. Won-Joon,Lee. Hi-Deok
- ㆍ 간행물명
- 전기전자재료학회논문지
- ㆍ 권/호정보
- 2005년|18권 11호|pp.1001-1006 (6 pages)
- ㆍ 발행정보
- 한국전기전자재료학회
- ㆍ 파일정보
- 정기간행물| PDF텍스트
- ㆍ 주제분야
- 기타
A new fabrication method is proposed to form the stacked polysilicon gate by nitridation in $N_2$ atmosphere using conventional LP-CVD system. Two step stacked layers with an amorphous layer on top of a polycrystalline layer as well as three step stacked layers with polycrystalline films were fabricated using the proposed method. SIMS profile showed that the proposed method would successfully create the nitrogen-rich layers between the stacked polysilicon layers, thus resulting in effective retardation of dopant diffusion. It was observed that the dopants in stacked films were piled-up at the interface. TEM image also showed clear distinction of stacked layers, their plane grain size and grain mismatch at interface layers. Therefore, the number of stacked polysilicon layers with different crystalline structures, interface position and crystal phase can be easily controlled to improve the device performance and reliability without any negative effects in nano-scale CMOSFETs.