- IC 신뢰성 향상을 위한 내장형 고장검출 회로의 설계 및 제작
- ㆍ 저자명
- 유장우,김후성,윤지영,황상준,성만영,Ryu. Jang-Woo,Kim. Hoo-Sung,Yoon. Jee-Young,Hwang. Sang-Joon,Sung. Man-Young
- ㆍ 간행물명
- 전기전자재료학회논문지
- ㆍ 권/호정보
- 2005년|18권 5호|pp.431-438 (8 pages)
- ㆍ 발행정보
- 한국전기전자재료학회
- ㆍ 파일정보
- 정기간행물| PDF텍스트
- ㆍ 주제분야
- 기타
In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.