We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2;2.0{ imes}l0^{13};cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2;1.0{ imes}l0^{13};cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.