This paper presents an ASER (Accelerated Soft Error Rate) integral model. The model is based on the facts that the generated EHP/s(electron hole pairs) are diminished after some residual range of the incident alpha particle, where residual range is a function of the incident angle and the capping layer thickness over the semiconductor junction. The ASER is influenced by the flux of the alpha particles, the junction area ratio, the alpha particle incident angle when the critical charge is same as the collected charge, and the sizes of the alpha source and the chip. The model was examined with 8M static RAM samples. The measured ASER data showed good agreement with the calculated values using the model. The ASER decreased exponentially with respect to the operational voltage. As the capping layer thickness increases up to $16{mu}m$, the ASER increases, and after that thickness, the ASER decreases. The ASER increased as the depth of BNW increased from $0{mu}m;to;4{mu}m$. and then saturated. The ASER decreased as the node capacitance increased from 2fF to 5fF.