This paper presents a methodology that accelerates estimating the system-level power consumption for on-chip bus of SoC platforms. The proposed power modeling can estimate the power consumption according to the change of a target SoC system. The proposed model comprises two parts: the one is power estimation of bus logics reflecting the architecture of the bus such as the number of bus layers, the other is to estimate the power consumed by the bus lines during data transmission. We designed the target multimedia SoC system, MPEG encoder as an example and evaluated power consumption using this model. The simulation result shows that the accuracy of the proposed model is over 92%. Thus, the proposed power model can be used to design of a high-performance/low-power multimedia SoC.