- 반응표면분석법에 의한 적층 칩 바리스터의 전기적 특성
- ㆍ 저자명
- 윤중락,정태석,최근묵,이석원,Yoon. Jung-Rag,Jeong. Tae-Seok,Choi. Keun-Mook,Lee. Seok-Weon
- ㆍ 간행물명
- 전기전자재료학회논문지
- ㆍ 권/호정보
- 2007년|20권 6호|pp.496-501 (6 pages)
- ㆍ 발행정보
- 한국전기전자재료학회
- ㆍ 파일정보
- 정기간행물| PDF텍스트
- ㆍ 주제분야
- 기타
In order to enhance sintering characteristics on the $ZnO-Pr_6O_{11}$ based multilayer chip varistors (MLVs), a response surface analysis using central composite design method were carried out. As a result, varistor voltage($V_{1mA}$), nonlinear coefficient ($alpha$), leakage current ($I_L$) and capacitance (C) were considered to be mainly affected by sintered temperature and holding time. MLVs sintered at $1200^{circ}C$ and above $1200^{circ}C$ revealed poor electrical characteristics, possibly due to the reaction between electrode materials(Pd) and $ZnO-Pr_6O_{11}$ based ceramics. On the sintering temperature range $1150{sim}1175^{circ}C$, nonlinear coefficient ($alpha$) and leakage current ($I_L$) were shown to be $60{sim}69$ and below $0.3{mu}A$, respectively. In particular, MLVs sintered at $1175^{circ}C$, 1.5 hr and $2^{circ}C/hr$ (cooling speed) showed stable ESD(Electrical Static Discharge) characteristics under the condition of 10 times at 8 Kv with deviation varistor voltage, and deviation nonlinear coefficient were 0.3% and 0.33% (at positive), 0.55% (at negative), respectively.