[ $0.35{mu}m$ ]twin-well non-epitaxial CMOS 공정에서의 substrate noise에 의한 아날로그 회로의 성능 저하를 예측하기 위하여 substrate 저항을 모델링하였다. Substrate 저항 모델 방정식은 P+ guard-ring isolation에 적용되어 측정값과 일치함을 확인하였다. Substrate 저항을 네 가지 형태로 구분하고 각각에 대하여 semi-empirical 모델 방정식을 확립하여, 측정값과 비교하여 rms 오차가 10% 미만이 되었다. 이 substrate 저항 모델을 guard-ring에 의한 isolation 구조에 적용하기 위하여 모델 방정식과 ADS(Advanced Design System) 회로 시뮬레이션에 의한 결과와 Network Analyzer의 측정 결과를 비교하였고, 비교적 잘 일치함을 확인하였다.
The substrate resistance is modeled to estimate the performance degradation of analog circuits by substrate noise in a $0.35{mu}m$ twin-well non-epitaxial CMOS process. The substrate resistance model equations are applied to the P+ guard-ring isolation structure and a good match was achieved between measurements and models. The substrate resistance is divided into four types and a semi-empirical model equation is obtained for each type of substrate resistance. The rms(root-mean-square) error of the substrate resistance model is below 10% compared with the measured resistance. To apply this substrate resistance model to the P+ guard ring structure, ADS(Advanced Design System) circuit simulation results are compared with the measurement results using Network Analyzer, and relatively good agreements are obtained between measurements and simulations.
