A multi-bit sigma-delta modulator architecture is described for low-distortion performance and a high-speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog-to-digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog-to-digital converter and the scrambler logic. Implemented by a 0.13 ${mu}m$ CMOS process, the sigma-delta modulator achieves high linearity. The measured spurious-free dynamic range is 89.1 dB for -6 dBFS input signal.