This research paper aims to establish a test process of the AFE SiP chip. It measured the sensitivity, current consumption and power consumption both on the evaluation socket board and Catalyst load board. As a result, the sensitivity became deteriorated with an average of 0.2[dBm] at the channel 62 only, the current consumption increased to an average of 0.57[mA] and the power consumption increased to an average of 1.76[mW], But all characteristics incomes the tolerance of the measurement, it also keeps almost the same level. Therefore this design of the test process improved a valid design.