This paper presents the implementation of a Tiling System about Preprocessing functions of JPEG 2000. The system covers the JPEG 2000 standard and is designed to determine the size of the image, to expand the image area and to split input image into several tiles. In order to split the input image with the progressive transmission into several tiles and transmit a tile of this image to others, this system store this image into Frame Memory. Therefore, this is designed as the Finite State Machine (FSM) to sequence through specific patterns of states in a predetermined sequential manner by using Verilog-HDL and be designed to handle a maximum 5M image. Moreover, for identifying image size for expansion, we propose several formula which are based on remainder after division (rem). we propose the true table which determines the size of the image input patterns by using results of these formula. Under the condition of TSMC 0.25um ASIC library, gate count is 18,725 and maximum data arrival time is 18.94 [ns].