In this paper, we deal with the TLP evaluation results for GGNMOS in ESD protection device of conventional CMOS process. An evaluation parameter for GGNMOS is that repeatability evaluation for reference device($W/L=50;{mu}m1.0;{mu}m$) and following factors for design as gate width, number of finger, present or not for N+ gurad -ring, space of N-field region to contact and present or not for NLDD layer. The result of repeatability was showed uniformity of lower than 1 %. The result for design factor evaluation was ; 1) gate width leading to increase It2, 2) An increase o( finger number was raised current capability(It2), and 3) present of N+ gurad-ring was more effective than not them for current sink. Finally we suggest the optimized design conditions for GGNMOS in evaluated factor as ESD protection device of conventional CMOS process.