In the TDMA PON system, the DBA is essential for ONUs to send data efficiently to the upstream. In this paper, we implement a DBA processor for the G-PON OLT with downstream and upstream rate, 2.5 and 1.25 Gbps, respectively, The processor collects bandwidth request messages from ONUs at every cycle time and allocates properly bandwidth to each Alloc-ID with considering priority and fairness for traffics. In the proposed DBA algorithm, one cycle time consists of multiple G-PON frames ($m{ imes}125{mu}s$) for high link efficiency. In particular, the link efficiency is higher because the algorithm adopts a method that an additional overhead is eliminated when an allocated bandwidth is laid between two G-PON frames for an ONU. This enables that the processor flexibly allocates the bandwidth from zero to the maximum link capacity for an ONU. The proposed DBA processor is implemented with the FPGA and shows bandwidth allocating processes for ONUs with logic analyzer.