In this paper, SI(Signal Integrity) characteristic of the 4-layer PCB(Printed Circuit Boards) with a through-hole via was analyzed by impedance mismatching between the through-hole via and the transmission line, and deterioration of clock pulse response characteristic due to the P/G plane resonances which are generated between the power and the ground plane. The minimized impedance mismatching between the through-hole via and the transmission line for the improving of SI characteristic is confirmed by the TDR(Time Domain Reflector) simulation and lumped element modeling of the through-hole via. And the cancellation method of P/G plane resonances for improvement of the SI characteristic is represented by simulation result.