Solution for network equations is frequently encountered by power system researchers. With the increasingly larger system size, time consumed network solution is becoming a dominant factor in the overall time cost. One distinct and important feature of the network admittance matrix is that it is highly sparse, which need to be addressed by specialized computation techniques. One technique to accelerate matrix factorization is parallel computation, with which data processing can be divided into different tasks and implemented simultaneously. However, up to now, efficiency of parallel computation algorithm implemented on multi-processor systems is adversely affected by the data communication latency between processors. In this paper, by taking advantage of the parallel computing power of the contemporary Graphic Processing Units (GPU) and designs of sparse technique for matrix factorization implemented on GPU, proposed algorithms are implemented and evaluated on the Computer Unified Device Architecture (CUDA) interface of the NVIDIA GPU. Preliminary results show significant improvement of speed of LU factorization.