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Direct Current (DC) Bias Stress Characteristics of a Bottom-Gate Thin-Film Transistor with an Amorphous/Microcrystalline Si Double Layer
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  • Direct Current (DC) Bias Stress Characteristics of a Bottom-Gate Thin-Film Transistor with an Amorphous/Microcrystalline Si Double Layer
  • Direct Current (DC) Bias Stress Characteristics of a Bottom-Gate Thin-Film Transistor with an Amorphous/Microcrystalline Si Double Layer
저자명
Jeong. Tae-Hoon,Kim. Si-Joon,Kim. Hyun-Jae
간행물명
Transactions on electrical and electronic materials
권/호정보
2011년|12권 5호|pp.197-199 (3 pages)
발행정보
한국전기전자재료학회
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정기간행물|ENG|
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이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

In this paper, the bottom-gate thin-film transistors (TFTs) were fabricated with an amorphous/microcrystalline Si double layer (DL) as an active layer and the variations of the electrical characteristics were investigated according to the DC bias stresses. Since the fabrication process of DL TFTs was identical to that of the conventional amorphous Si (a-Si) TFTs, it creates no additional manufacturing cost. Moreover, the amorphous/microcrystalline Si DL could possibly improve stability and mass production efficiency. Although the field effect mobility of the typical DL TFTs is similar to that of a-Si TFTs, the DL TFTs had a higher reliability with respect to the direct current (DC) bias stresses.