In this paper, the trade-off related to bandwidth of high-speed common-mode logic frequency divider is analyzed in detail. A method to optimize the operating frequency, band-width as well as power consumption is proposed. This method is based on bipolar device characteristics, whereby a negative resistance model can be used to estimate the optimal normalized upper frequency and lower frequency of frequency dividers under different conditions, which is conventionally ignored in literatures. This method provides a simple but efficient procedure in designing high performance frequency dividers for different applications. To verify the proposed method, a static divide-by-2 at millimeter wave ranges is implemented in 180 nm SiGe technology. Measurement results of the divider demonstrate significant improvement in the figure of merit as compared with literatures.