This paper describes the design of a high-performance unified SVM classifier circuit. The proposed circuit supports both linear and non-linear SVM classifications. In order to ensure efficient classification, a 48x96 or 64x64 sliding window with 20 window strides is used. We reduced the circuit size by sharing most of the resources required for both types of classification. We described the proposed unified SVM classifier circuit using the Verilog HDL and synthesized the gate-level circuit using 65nm standard cell library. The synthesized circuit consists of 661,261 gates, operates at the maximum operating frequency of 152 MHz and processes up to 33.8 640x480 image frames per second.