This paper proposes a $16{ imes}16$ and $32{ imes}32$ inverse transform architecture for HEVC (High Efficiency Video Coding). HEVC large transform of $16{ imes}16$ and $32{ imes}32$ suffers from huge computational complexity. To resolve this problem, we proposed a new large inverse transform architecture based on hardware reuse. The processing element is optimized by exploiting fully recursive and regular butterfly structure. To achieve low area, the processing element is implemented by shifters and adders without multiplier. Implementation of the proposed 2-D inverse transform architecture in 0.18 ${mu}m$ technology shows about 300 MHz frequency and 287 Kgates area, which can process 4K ($3840{ imes}2160$)@ 30 fps image.