This paper presents a design and fabrication of 0.5 V two stage operational amplifier. The proposed operational amplifier utilizes body-driven differential input stage and self-cascode current mirror structure. Cadence Virtuoso is used for layout and the layout data is verified by LVS through Mentor Calibre. The proposed two stage operational amplifier is fabricated using $0.13{mu}m$ CMOS process and operation at 0.5 V is confirmed. Measured low frequency small signal gain of operational amplifier is 50 dB, power consumption is $29{mu}W$ and chip area is $75{mu}m{ imes}90{mu}m$.