In this paper, the FLL(Frequency Locked Loop) circuit using current conveyor circuit is designed by $0.35{mu}m$ CMOS process. The FLL circuit is built in a frequency divider, a frequency-to-voltage converter, a voltage subtractor and a oscillator and the circuit blocks have a symmetric structure to improve a reliability characteristics with a process variation. From the simulation results, the variation rate of output frequency is about less than ${pm}1%$ when the channel length, channel width, resistance and capacitance are varied ${pm}5%$.