This paper presents a clock regenerator using two $2^{nd}$ order ${sum}-{Delta}$ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different ${sum}-{Delta}$ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 ${mu}m$ CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.