This paper proposes and implements an core transform architecture, which is one of the major processes in HEVC video compression standard. The proposed core transform architecture is implemented with only adders and shifters instead of area-consuming multipliers. Shifters in the proposed core transform architecture are implemented in wires and multiplexers, which significantly reduces chip area. Also, it can process from $4{ imes}4$ to $16{ imes}16$ blocks with common hardware by reusing processing elements. Designed core transform architecture in 0.13um technology can process a $16{ imes}16$ block with 2-D transform in 130 cycles, and its gate count is 101,015 gates.